1. Technical Field
Various embodiments of the present invention relate to methods of fabricating fine patterns and, more particularly, to methods of fabricating interconnection structures.
2. Related Art
In the fabrication of integrated circuit (IC) devices, much effort has been focused on integrating finer patterns within a limited area on a semiconductor substrate. That is, attempts to increase the integration density of semiconductor devices have typically resulted in the formation of finer patterns. Various techniques have been proposed to form finer patterns such as small contact holes having nano-scale critical dimensions (CD), for example, from a few nanometers to tens of nanometers.
When the patterns are formed using only a photolithography process, there are some limitations in how fine the patterns may be. Image resolution limitations are due to the nature of the optical systems as well as the wavelength of exposure light used during the photolithography process. Methods of forming finer patterns using self-assembly of polymers are candidates for overcoming the image resolution limits.
Interconnection structures in semiconductor devices include conductive lines extending in a horizontal direction and conductive vias extending in a vertical direction. A dual damascene process scheme has been used to form the conductive lines and the conductive vias or contact plugs, with a filling and planarization technique using a single metal material. The dual damascene process scheme that is known in the art requires two separate lithography process steps for forming a trench in a substrate and a via hole that is spatially connected to the trench. To fabricate high performance semiconductor chips, it is necessary to densely form discrete elements such as transistors and metal lines in a limited area, requiring accurate photo masks. For example, the overlay tolerance between two photo masks used in two separate lithography process steps must be accurately controlled. These requirements make it difficult to fabricate high performance semiconductor chips using the dual damascene process. That is, if high performance semiconductor chips are fabricated using the lithography processes, manufacturing costs may increase.